1. Field of the Invention
The present invention generally relates to computer systems, and in particular, to a prefetch buffer allocation and filtering system.
2. Description of the Related Art
In conventional computer systems, instructions and data required by a processor may be retrieved from a main memory. However, the latency involved with retrieving information from the main memory can impose a burden on system performance. To improve system performance, prefetching techniques may be implemented to prefetch instruction/data into a faster memory device prior to the time the instruction/data is requested by the processor. In some implementations, the faster memory device may comprise a prefetch buffer located external to the processor so that the buffer can be loaded without effecting the bandwidth of the processor bus coupling the processor to the rest of the system.
Prefetching techniques require information from the main memory to be speculatively fetched into the prefetch buffers based on the principle that if a memory location is addressed by the processor, the next sequential address will likely be requested by the processor in the near future. However, speculative prefetch requests dispatched in an attempt to supply memory data to the prefetch buffer ahead of time to reduce latency may adversely effect system performance by reducing available bandwidth of a memory bus that provides a communications link between the main memory and the prefetch buffers, causing subsequent non-speculative fetch requests to wait for the speculative prefetch requests.